1. Field of the Invention
This invention relates to an arithmetic circuit for performing a variety of multiple data input operations that are useful, for example, in video encoding and decoding.
2. Description of Related Art
Video encoding and decoding typically requires repetitive calculation which manipulate relatively large amounts of data that is often arranged in two dimensional data arrays such as pixel maps. Processing architectures which process one data element (or pixel) at a time can be slow for video encoding and decoding because of the large number of data elements which must be processed. Accordingly, vector processing architectures have been developed which perform multiple simultaneous operations in parallel on multiple data elements. For example, in a single instruction multiple data (SIMD) architecture, a processor performing a single instruction performs the same operation on multiple data elements in parallel.
Additionally, video processing of each data element typically requires more than one basic arithmetic operations. For example, taking an average of four pixel values requires three additions and one division (or rounding), and a process only capable of basic arithmetic operations such as shifts, rotates, addition, subtraction, multiplication, and division may require four instructions to complete an average. A special arithmetic circuit can be implemented for specific operations, but adding such special circuits to a processor increases the processor's size and cost. Additionally, implementing specific hardware for each of a large number of complex tasks used in video encoding and decoding is impractical because it greatly increases the complexity of the processor which can harm performance. A processing architecture is thus sought which quickly performs a large variety of complex task used in video encoding and decoding but does not greatly increase circuit complexity.